1. Field of the Invention
The present invention relates to a data conversion apparatus which handles code data, and a control method thereof.
2. Description of the Related Art
In order to reduce a bus width required for data transfer and an area required for data storage in a system that handles a data sequence, a technique for compressing data by encode processing prior to data transfer or storage is available. Processing that restores data when the contents of that data are required is decode processing.
Various kinds of encoding formats are available. However, as for document image data in which identical pixel values often run, a runlength encoding format which can be implemented by a simple and low-cost hardware arrangement is normally adopted. At this time, when one pixel is expressed by 1 byte, it is a common practice to attain runlength compression for respective bytes using 1 byte as length information.
On the other hand, the data size of image data used in a print operation of a printer (or printer engine) is also reduced by the aforementioned data encode/decode processing. In this case, encoded image data is decoded to catch up timings at which the printer requires data, and the decoded data is sequentially transferred to the printer. That is, the decode processing requires realtimeness. For this reason, in order to prevent data used in the print operation from being omitted, the decode processing speed has to be equal to or higher than the data request speed of the printer.
Processing for decoding runlength-encoded code data is sequential processing for respective unit codes composing the code data. This is because the runlength-encoded code data includes a run of a plurality of sets of length information and data information, and the runlength encoding is a variable length encoding method in which the number of pieces of subsequent data information is determined depending on the contents of the length information. Each set is called a unit code. In order to find the next length information, previous length information has to be evaluated, and simple parallel processing cannot be executed.
On the other hand, the number of data that can be output by evaluating one length information is variable, and is normally 1 in case of the minimum number of data. Therefore, the processing speed of a decoding circuit which operates in synchronism with clocks is 1 data/cycle in case of the minimum number of data. For example, upon decoding code data runlength-encoded for 1-byte units, the processing speed is 1 byte/cycle in case of the minimum number of data. When this processing speed is expressed by a throughput (a data size that can be processed per unit time), a minimum throughput is 1 or simply, a throughput is 1.
In recent years, since the printer technology has been improved, printers which can execute print operations with higher resolutions and higher speeds than the conventional printers are available. When the resolution and print speed become higher, a data size required for a print operation per unit time also becomes larger, and a data size to be transferred to a printer inevitably increases. Some high-resolution or high-speed printers require data transfer of, for example, six data per cycle. In this case, the processing speed of runlength decoding (throughput=1) is lower than the data request speed of a printer (throughput=6). For this reason, with an arrangement which simply decodes data in real time and transfers decoded data to a printer, the data transfer speed to the printer cannot catch up the data request speed.
For this reason, a technique which decodes code data in advance, stores decoded data in an intermediate buffer, and reads out and transfers the decoded data from the intermediate buffer in response to a request from a printer so as to avoid any data omissions may be used. Or a method which drives a decoding circuit using a clock signal having a frequency six times that of a data transfer circuit to configure a circuit that allows to decode six data per data transfer cycle may be used. Or a technique that simultaneously decodes a plurality of unit codes (sets of length information and data information) as many as the number of unit codes required to achieve a target throughput has been proposed (for example, Japanese Patent Laid-Open No. 2007-189527).
However, since the intermediate buffer in the aforementioned related art is implemented by a page memory device that stores a data size required by a printer for one print operation, it requires considerably high cost. Also, driving using the clock signal having the frequency six times that of the data transfer circuit requires high cost. This is because use of the frequency six times the operation frequency of the data transfer circuit requires high technical difficulties in terms of the semiconductor physical design, manufacturing technique, and manufacture.
With the technique which simultaneously expands a plurality of unit codes (sets of length information and data information) in a number as large as the number of unit codes required to achieve a target throughput in the aforementioned related art, when a circuit is configured to realize a throughput=6, the circuit scale and operation speed pose problems. This is because the above technique determines an operation by collating the alignment sequence of length information of input code data with a plurality of patterns which are stored in advance, but the number of patterns increases combinatorially. More specifically, in an arrangement that realizes a throughput=4, the number of patterns is 41. However, for example, in an arrangement that realizes a throughput=6, the number of patterns is 239, and a large circuit scale and a long processing delay time of a pattern matching circuit with input data are required. When the circuit scale increases, cost also increases, and when the processing delay time becomes longer, it technically becomes difficult to process data within one cycle, resulting in high cost.